www.lansdale.com page 1 of 8 issue a ml145403 ml145404 ml145405 ml145408 drivers/receivers rs 232/eia?32? and ccitt v.28 legacy device: motorola mc145403, mc145404, mc145405, mc145408 these devices are silicon gate cmos ics that combine both the transmitter and receiver to fulfill the electrical specifications of eia standard 232? and ccitt v.28. the drivers feature true ttl input compatibility, slew rate limiting outputs, 300 power?ff source impedance, and output typically switching to within 25% of the sup- ply rails. the receivers can handle up to 25 v while presenting 3 to 7 k impedance. hysteresis in the receivers aid in the reception of noisy signals. by combining both drivers and receivers in a single cmos chip, these devices provide efficient, low?ower solutions for both eia?32? and v.28 applications. these devices offer the following performance features: ? operating temperature range t a = ?0 to +85? drivers ? 5 to 12 v supply range ? 300 power?ff source impedance ? output current limiting ? ttl and cmos compatible inputs ? driver slew rate range limited to 30 v/? maximum receivers ? 25 v input range ? 3 to 7 k input impedance ? 0.8 v of hysteresis for enhanced noise immunity ? ttl and cmos compatible outputs note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . available driver/receiver combinations device drivers receivers figure no. of pins ml145403 3 5 1 20 ml145404 4 4 2 20 ml145405 5 3 3 20 ml145408 5 5 4 24 alternative eia?32 devices to consider are: three supply single supply ml145406 (3 x 3) ml145407 (3 x 3)
www.lansdale.com page 2 of 8 issue a lansdale semiconductor, inc. ml145403, ml145404, ml145405, ml145408 ml145403 3 drivers/5 receivers r r d d r d v dd rx1 tx1 rx2 rx3 tx2 rx4 rx5 tx3 v ss v cc do1 di1 do2 do3 di2 do4 do5 di3 gnd 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 pin assignments (dip and sog) ml145404 4 drivers/4 receivers r r r d d r d d v dd rx1 tx1 rx2 tx2 rx3 tx3 rx4 tx4 v ss v cc do1 di1 do2 di3 do3 di3 do4 di4 gnd 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ml145405 5 drivers/3 receivers r d d r d d v dd rx1 tx1 tx2 rx2 tx3 tx4 rx3 tx5 v ss v cc do1 di1 di2 do2 di3 di4 do3 di5 gnd 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 r d r d r d r d r d v dd rx1 tx1 rx2 tx2 rx3 tx3 rx4 tx4 rx5 1 2 3 4 5 6 7 8 9 10 di1 do2 di2 do3 di3 do4 di4 do5 di5 gnd 22 21 20 19 18 17 16 15 14 13 24 23 11 12 v cc do1 v ss tx5 ml145408 5 drivers/5 receivers r r r d functional diagram esd protection + do rx 5.4 k 15 k v dd v ss v cc tx 300 + level shift 1.0 v 1.8 v v cc di 1.4 v v cc v ss receiver driver v dd +
www.lansdale.com page 3 of 8 issue a absolute maximum ratings (voltages referenced to gnd, except where noted) rating symbol value unit dc supply voltage (v dd v cc ) v dd v ss v cc ?0.5 to + 13.5 + 0.5 to ?13.5 ?0.5 to + 6.0 v input voltage range rx1 ?rx n di1 ?di n v ir v ss ?15 to v dd + 15 0.5 to v cc + 15 v dc current drain per pin i 00 ma power dissipation p d 1 w operating temperature range t a ?40 to + 85 c storage temperature range t stg ?85 to + 150 c dc electrical characteristics (all polarities referenced to gnd = 0 v, t a = ?40 to + 85 c) parameter symbol min typ max unit dc supply voltage v dd v ss v cc 4.5 ?4.5 4.5 5 to 12 ?5 to ?12 5 13.2 ?13.2 5.5 v quiescent supply current (outputs unloaded, inputs low) v dd = + 12 v v ss = ?12 v v cc = + 5 v i dd i ss i cc 425 ?400 110 635 ?600 200 a receiver electrical specifications (voltage polarities referenced to gnd = 0 v, v dd = + 12 v, v ss = ?12 v, t a = ?40 to + 85 c, v cc = + 5 v, 10%) characteristic symbol min typ max unit input turn?n threshold rx1 ?rx n v do = v ol v on 1.35 1.8 2.35 v input turn?ff threshold rx1 ?rx n v do = v oh v off 0.75 1 1.25 v input threshold hysteresis ? = v on ?v off v hys 0.6 0.8 v input resistance (v ss ?15 v) v rx1 ?rx n (v dd + 15 v) r in 3 5.4 7 k high level output voltage i out = ?20 a v rx = 3 to ?25 v* (do1 ?do n )i out = ?1.0 ma v oh 4.9 3.8 4.9 4.3 v low level output voltage i out = + 2 ma v rx = + 3 to + 25 v* (do1 ?do n )i out = + 4 ma v ol 0.02 0.5 0.5 0.7 v * this is the range of input voltages as specified by eia?32? to cause a receiver to be in the high or low. this device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high imped- ance circuit. for proper operation it is recommended that v out and v in be constrained to the ranges described as follows: digital i/o: driver inputs (di): (gnd v di v cc ). receiver outputs (do): (gnd v do v cc ). eia?32 i/o: driver outputs (tx): (v ss v tx1 tx n v dd ). receiver inputs (rx): v ss ?15 v v rx1 rx n v dd + 15 v). reliability of operation is enhanced if unused outputs are tied off to an appropriate logic voltage level (e.g., either gnd or v cc for di, and gnd for rx). lansdale semiconductor, inc. ml145403, ml145404, ml145405, ml145408
www.lansdale.com page 4 of 8 issue a lansdale semiconductor, inc. ml145403, ml145404, ml145405, ml145408 driver electrical specifications (voltage polarities referenced to gnd = 0 v, v dd = + 12 v, v ss = ?12 v, t a = ?40 to + 85 c, v cc = + 5 v, 10%) characteristic symbol min typ max unit digital input voltage di1 ?di n logic 0 logic 1 v il v ih 2 0.8 v input current di1 ?di n v di = gnd v di = v cc i il i ih 7 1.0 a output high voltage tx1 ?tx n v di = logic 0, r l = 3 k v dd = + 5.0 v, v ss = ?5.0 v v dd = + 6.0 v, v ss = ?6.0 v v dd = + 12.0 v, v ss = ?12.0 v v oh 3.5 4.3 9.2 3.9 4.7 9.5 v output low voltage* tx1 ?tx n v di = logic 1, r l = 3 k v dd = + 5.0 v, v ss = ?5.0 v v dd = + 6.0 v, v ss = ?6.0 v v dd = + 12.0 v, v ss = ?12.0 v v ol ?4 ?4.5 ?10 ?4.3 ?5.2 ?10.3 v input current tx1 ?tx n (figure 5) z off 300 output short circuit current tx1 ?tx n v dd = + 12 v, v ss = ?12 v tx shorted to gnd** tx shorted to 15 v*** i sc 22 60 60 100 ma * voltage specifications are in terms of absolute values. ** specification is for one tx output pin to be shorted at a time. should all three driver outputs be shorted simultaneously, de vice power dissipation limits will be exceeded. *** this condition could exceed package limitations. switching characteristics (v cc = + 5 v, 10%, v dd = + 12 v, v ss = ?12 v, t a = ?40 to + 85 c; see figures 2 and 3) characteristic symbol min typ max unit drivers propagation delay time tx low?o?igh r l = 3 k , c l = 50 pf t plh 500 1000 ns high?o?ow r l = 3 k , c l = 50 pf t phl 700 1000 output slew rate minimum load r l = 7 k , c l = 0 pf (v dd = 6 to 12 v, v ss = ?6 to ?12 v) sr 6 30 v/ s maximum load r l = 3 k , c l = 2500 pf (v dd = 12 v, v ss = ?12 v, v cc = 5 v) 4 receivers (c l = 50 pf) propagation delay time low?o?igh t plh 360 610 ns high?o?ow t phl 130 610 output rise time t r 250 400 ns output fall time t f 40 100 ns
www.lansdale.com page 5 of 8 issue a p in d e scri p tions vcc digital p ower supply the digital supply pin, which is connected to the logic power supply (+ 5.5 v maximum). gnd ground ground return pin is typically connected to the signal ground pin of the eia?32? connector (pin 7) as well as to the logic power supply ground. vdd most p ositive device p in the most positive power supply pin, which is typically + 5 to + 12 v. vss most negative device p in the most negative power supply pin, which is typically 5 to 12 v. rx1 ?rxn receive data input p ins these are the eia?32? receive signal inputs. a voltage between + 3 and + 25 v is decoded as a space, and causes the corresponding do pin to swing to ground (0 v). a voltage between ?3 and ?25 v is decoded as a mark, and causes the corresponding do pin to swing to v cc . do1 ?don data output p ins these are the receiver digital output pins which swing fromv cc to gnd. each output pin is capable of driving one lsttl input load. lansdale semiconductor, inc. ml145403, ml145404, ml145405, ml145408 figure 1. power?ff source resistance illustrated for ml145408 di5 14 1 24 11 v dd 16 18 20 22 9 3 5 7 13 12 gnd v dd v cc di4 di3 di2 di1 tx5 tx4 tx3 tx2 tx1 v in = 2 v r out v in i figure 2. switching characteristics 50% di + 3 v 0 v t f 10% 90% t r t phl t plh v ol v oh tx drivers 50% rx + 3 v 0 v t f 10% 90% t r t phl t plh v ol v oh do receivers figure 3. slew rate characteristics tx + 3 v t shl drivers + 3 v t slh 3 v 3 v slew rate = 6 v t slh or t shl
www.lansdale.com page 6 of 8 issue a lansdale semiconductor, inc. ml145403, ml145404, ml145405, ml145408 di1 ?din data input p ins these are the high impedance digital input pins to the driv- ers. input voltage levels on these pins are lsttl compatible and must be between v cc and gnd. a weak pull?p on each input sets all unused di pins to v cc , causing the correspon- ding unused driver outputs to be at v ss . tx1 ?txn transmit data output p ins these are the eia?32? transmit signal output pins, which swing from v dd to v ss . a logic 1 at the di input causes the corresponding tx output to swing to v ss . a logic 0 at the di input causes the corresponding tx out to swing to v dd . the actual levels and slew rate achieved will depend on the output loading (r l// c l ). l e gacy a pp lication information p ow e r su pp ly consid e rations figure 4 shows a technique to guard against excessive de- vice current. the diode d1 prevents excessive current from flowing through an internal diode from the v cc pin to the v dd pin- when v dd < v cc by approximately 0.6 v or greater. this high current condition can exist for a short period of time dur- ing power up/down. additionally, if the + 12 v supply is switched off while the + 5 v is on and the off supply is a low impedance to ground, the diode d1 will prevent current flow through the internal diode. the diode d2 is used as a voltage clamp, to prevent v ss from drifting positive to v cc , in the event that power is re- moved from v ss (pin 12). if v ss power is removed, and the impedance from the v ss pin to ground is greater than approxi- mately 3 k , this pin will be pulled to v cc by internal circuit- ry causing excessive current in the v cc pin. if by design, neither of the above conditions are allowed to exist, then the diodes d1 and d2 are not required. e sd p rot e ction ? caution esd protection on ic devices that have their pins accessible to the outside world is essential. high static voltages applied to the pins when someone touches them either directly or in directly can cause damage to gate oxides and transistor junc- tions by coupling a portion of the energy from the i/o pin to the power supply buses of the ic. this coupling will usually occur through the internal esd protection diodes. the key to protecting the ic is to shunt as much of the energy to ground as possible before it enters the ic. figure 4 shows a technique which will clamp the esd voltage at approximately 15 v using the mmbz15vdlt1. any residual voltage which appears on the supply pins is shunted to ground through the capacitors c1 ?c3. this scheme has provided protection to the interface part up to 10kv, using the human body model test. r r r r r v dd rx1 tx1 rx2 tx2 rx3 tx3 rx4 tx4 rx5 1 2 3 4 5 6 7 8 9 10 di1 do2 di2 do3 di3 do4 di4 do5 di5 gnd 22 21 20 19 18 17 16 15 14 13 24 23 11 12 v cc do1 v ss tx5 + 5 v c2 d1 c3 ?12 v 1n5818 1n4001 d2 c1 + 12 v 1n4001 d d d d d figure 4. mmbz15vdlt1 x 10
www.lansdale.com page 7 of 8 issue a lansdale semiconductor, inc. ml145403, ml145404, ml145405, ml145408 outline dimensions p dip 20 = rp (ml145403rp, ml145404rp, ml145405rp) plastic dip case 738?3 1.070 0.260 0.180 0.022 0.070 0.015 0.140 15 0.040 1.010 0.240 0.150 0.015 0.050 0.008 0.110 0 0.020 25.66 6.10 3.81 0.39 1.27 0.21 2.80 0 0.51 27.17 6.60 4.57 0.55 1.77 0.38 3.55 15 1.01 0.050 bsc 0.100 bsc 0.300 bsc 1.27 bsc 2.54 bsc 7.62 bsc min min max max inches millimeters dim a b c d e f g j k l m n notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. -a- c k n e gf d 20 pl j 20 pl l m -t- seating plane 1 10 11 20 0.25 (0.010) t a m m 0.25 (0.010) t b m m b p dip 24 = lp (ml145408lp) plastic dip case 724?3 notes: 1. chamfered contour optional. 2. dimension l to center of leads when formed parallel. 3. dimensioning and tolerancing per ansi y14.5m, 1982. 4. controlling dimension: inch. ? ? 24 13 12 1 ? seating plane 24 pl k e f n c d g m a m 0.25 (0.010) t 24 pl j m b m 0.25 (0.010) t l m note 1 dim min max min max millimeters inches a 1.230 1.265 31.25 32.13 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.020 0.38 0.51 e 0.050 bsc 1.27 bsc f 0.040 0.060 1.02 1.52 g 0.100 bsc 2.54 bsc j 0.007 0.012 0.18 0.30 k 0.110 0.140 2.80 3.55 l 0.300 bsc 7.62 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.01
www.lansdale.com page 8 of 8 issue a lansdale semiconductor, inc. ml145403, ml145404, ml145405, ml145408 so 20w = -6p (ml145403-6p, ml145404-6p, ml145405-6p) outline dimensions sog package case 751d?4 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? ? 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c ? seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 so 24w = -6p (ml145408-6p) sog package case 751e?4 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? ? p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t ? g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 lansdale semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili- ty, function or design. lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. ?ypical parameters which may be provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by the customer s technical experts. lansdale semiconductor is a registered trademark of lansdale semiconductor, inc.
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